A semiconductor device can include integrated circuits with particular feature sizes. The feature sizes can be reduced in order to increase portability, computing power, memory capacity and/or energy efficiency. Reduced feature sizes for integrated circuits can be related to techniques used to form the features. For example, lithography can be used to pattern features (e.g., conductive lines) of integrated circuits. The periodicity of these patterned features can be described as pitch.
Pitch can be described as a distance between points of two neighboring features. Lithographic techniques may not reliably form features below a minimum pitch due to factors such as optics and/or light or radiation wavelength. Thus, the minimum pitch of a lithographic feature can be an obstacle to feature size reduction. As an example, when a pitch is halved, this reduction can be referred to as pitch doubling, and when pitch is quartered, this reduction can be referred to as pitch quadrupling or pitch quad.
Previous approaches to pitch doubling and/or pitch quadrupling can include transferring (e.g., etching) a particular pattern (e.g., a pattern of spacers) onto a number of hard mask layers (sometimes consisting of carbon) a number of times (once for a pitch doubling or repeated more than once for pitch quadrupling). These previous approaches can be costly to etch multiple patterns into multiple hard mask layers. In addition, forming non-square spacers (e.g., spacers having rounded corners) can reduce the quality of patterns transferred to underlying materials, which can lead to various negative effects.